#Generate a test bench with modelsim pe verification
When creating a verification algorithm, you should always try to implement the test differently than in the DUT. The testbench will print out “Test: OK”, regardless if the output is correct or not. Now we are supplying the DUT with inputs, but there is no checking of the output at all. Add the “-onfinish stop” switch to the Vsim command, as described in the ModelSim command reference. This behavior may be changed when launching Vsim from a script or from the command line. Note that if you run ModelSim with the default Run-button, ModelSim will prompt you with the quit dialog after the testbench completes successfully. The text “Test: OK” is printed to the console, and then the simulation is stopped by using the VHDL-2008 keyword “finish”.
#Generate a test bench with modelsim pe code
The final two code lines within the process is for ending the test gracefully. After that, there is no need for further testing because the DUT will just continue to yield the same results over and over again. The second chunk of code is for testing the situation where the input counter goes back to 0, which was the initial input value. Although, any nanosecond value greater than 0 would have worked, because the logic inside of the DUT is purely combinational. In between the values, we wait for 10 nanoseconds to allow the DUT to react. The first code chunk is a For loop which generates the counting sequence from the lowest possible value to the highest possible value. The code below contains the entire process for generating the input sequence. However, I will make an educated guess that testing with vector lengths of four bits is enough to reveal any possible issue with this module. The input and outputs of our DUT is of unspecified range. Although, if there are too many permutations, you may be restricted to doing only corner cases. It’s always best to create an exhaustive test, a test that tries all possible input values. Our next addition to the testbench will be the process that generates inputs for the DUT. You always want to be able to use the latest VHDL constructs in your testbench, but most synthesis tools don’t support them. It’s normal to use a higher version of VHDL for testbenches than for the RTL modules. You don’t need to change anything for the DUT. vhd file and select Properties→VHDL→Use 1076-2008->OK. Enable VHDL-2008įortunately, this can easily be fixed by setting the VHDL version for the testbench file to VHDL-2008. Package "STD.ENV" does not exist in this language version. If you try to compile the testbench in ModelSim without changing anything, you will get the following error: # ** Warning: gray_converter_tb.vhd(6): (vcom-1516) Note that we are importing which requires VHDL-2008. Signal gray : std_logic_vector(3 downto 0)
For that I have created the module in the code below. Let’s jump right in and create an example of a self-checking testbench.
We all know that stuff can break, and your best tool for catching these problems is the self-checking testbench. For example, when you make changes to the DUT, a sub-module, or an interfacing module. It’s important to be able to verify that all modules have the intended behavior at any time.
The self-checking testbench runs entirely on its own, and prints an “OK” or “Failed” message in the end.Įvery VHDL module should have an associated self-checking testbench. A self-checking testbench is a VHDL program that verifies the correctness of the device under test (DUT) without relying on an operator to manually inspect the output.
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